A typical example of the programmable logic array is illustrated in FIG. 1 of the drawings. The programmable logic array is associated with a plurality of ground level lines 1, a plurality of power supply lines 2, a precharging line 3 propagating a precharging signal, a plurality of complementary precharging lines 4 each propagating a complementary signal of the precharging signal, a control signal line 5 for a control signal, input signal lines 6 and 7, and output signal lines 8 and 9. All of the lines 1 to 9 extend in parallel to one another. The programmable logic array is further associated with a plurality of product lines 11, 12, 13, 14, 15 and 16, and the product lines 11 to 13 and 14 to 16 are provided in association with an AND plane 17 and an OR plane, respectively.
The AND plane is formed by using n-channel type field effect transistors 21, 22, 23 and 24, and the n-channel type field effect transistors 21 and 22 are coupled between the ground line 1 and the product lines 11 and 12, respectively. However, the n-channel type field effect transistors 23 and 24 are coupled between the ground line 1 and the product lines 12 and 13, respectively. The n-channel type field effect transistors 21 and 22 are gated by the input signal line 6, and, on the other hand, the n-channel type field effect transistors 23 and 24 are coupled at the gate electrodes thereof to the input signal line 7. All of the product lines 11, 12 and 13 are simultaneously precharged to a positive high voltage level Vcc through p-channel type field effect transistors 25, 26 and 27 with the complementary precharging signal of a low voltage level on the line 4.
The programmable logic array is further provided with n-channel type field effect transistors 28, 29 and 30 respectively gated by the product lines 11, 12 and 13, and the n-channel type field effect transistors 28, 29 and 30 are coupled between the control signal line 5 and intermediate nodes 31, 32 and 33, respectively.
On the other hand, the OR plane is formed by n-channel type field effect transistors 34, 35 and 36 the gate electrodes of which are coupled to the product lines 14, 15 and 16, respectively. The n-channel type field effect transistors 34 and 36 are coupled in parallel between the ground line 1 and the output signal line 8, but the n-channel type field effect transistor 35 is coupled between the ground line 1 and the output signal line 9. For a precharging operation of the intermediate nodes 31, 32 and 33, p-channel type field effect transistors 37, 38 and 39 are coupled between the power source line 2 and the intermediate nodes 31, 32 and 33, respectively, and the p-channel type field effect transistors 37, 38 and 39 are simultaneously gated by the complementary precharging line 4. N-channel type field effect transistors 40, 41 and 42 are provided in association with the product lines 14, 15 and 16 and coupled between the ground line 1 and the product lines 14, 15 and 16. The n-channel type field effect transistors 40, 41 and 42 are coupled at the gate electrodes thereof to the precharging line 3 for discharging the product lines 14, 15 and 16. The control signal line 5 is coupled to an inverter circuit 46 which is responsive to a control signal and provides a conduction path between a source of the positive voltage level and the control signal line 5, the inverter circuit 46 is formed by a series combination of a p-channel type field effect transistor and an n-channel type field effect transistor coupled between the source of positive voltage Vdd and the ground terminal.
Description is made for an operation of the programmable logic array with reference to FIG. 2 of the drawings. In FIG. 2, alphabetic letters "H" and "L" are indicative of the high voltage level and the low voltage level, respectively. If the programmable logic array is shifted into a precharging mode of operation at time t1, the precharging signal line 3 goes up to the high voltage level and the complementary precharging lines 4 conversely go down to the low voltage level. At time t1, when the inverter circuit 46 provides the conduction path between the source of positive voltage level and the control signal line 5 with the control signal of the low voltage level, the control signal line 5 is increased in voltage level, but the both of the input signal lines 6 and 7 are decreased to the low voltage level. With the low voltage level on the complementary signal line 4, the p-channel type field effect transistors 25, 26 and 27 simultaneously turn on to provide conduction paths between the power supply line 2 and the product lines 11, 12 and 13, respectively, and, accordingly, all of the product lines 11 to 13 are gradually precharged to the high voltage level. On the contrary, the product lines 14, 15 and 16 are discharged to the low voltage level, because the n-channel type field effect transistors 40, 41 and 42 provide conduction paths between the product lines 14 to 16 and the ground line 1.
The low voltage level is supplied from the input signal lines 6 and 7 to the n-channel type field effect transistors 21, 22, 23 and 24, so that no n-channel type field effect transistor turns on, thereby allowing the product lines 11 to 13 to remain in the high voltage level. This results in that all of the n-channel type field effect transistors 28, 29 and 30 turn on to provide conduction paths between the control signal line 5 and the respective intermediate nodes 31, 32 and 33.
At time t1, the control signal line 5 begins to rise to the high voltage level as described hereinbefore, and the n-channel type field effect transistors 28 to 30 in the on-states are transparent for the high voltage level on the control signal line 5. The intermediate nodes 31, 32 and 33 have been precharged in the presence of the low voltage level on the complementary precharging line 4, and no fluctuation in voltage level takes place at the intermediate nodes 31 to 33. With the high voltage level at the intermediate nodes 31 to 33, the p-channel type field effect transistors 43, 44 and 45 remain in the respective off-states, so that product lines 14 to 16 also remain in the low voltage level. If the product lines 14 to 16 keep low, no n-channel type field effect transistor turns on, so that the output signal lines 8 and 9 remain in the high voltage level. In this manner, the precharging operation is completed at time t2.
After the precharging operation, the input signal lines 6 and 7 are changed in voltage level depending upon input data bits supplied thereto. In this access, the input signal line 7 is assumed to be changed to the high voltage level, and, for this reason, the n-channel type field effect transistors 23 and 24 turn on to discharge the product lines 12 and 13, however, the n-channel type field effect transistor 21 remains off in the presence of the low voltage level on the input signal line 6. Then, the product line 11 allows the n-channel type field effect transistor 28 to be turned on for keeping the conduction path between the intermediate node 31 and the control line 5, however, the product lines 12 and 13 in the low voltage level cause the n-channel type field effect transistors 29 and 30 to turn off for blocking the conduction paths between the control signal line 5 and the intermediate nodes 32 and 33.
At time t3, the control signal line 5 is decreased in voltage level due to the control signal of the high voltage level applied to the inverter circuit 46, and, accordingly, the intermediate node 31 goes down to the low voltage level. However, the n-channel type field effect transistors 29 and 30 in the off-states prevent the respective intermediate nodes 32 and 33 from propagation of the low voltage level on the control signal line 5. When the intermediate node 31 is in the low voltage level, the pmos 43 turns on to charge the product line 14 toward the high voltage level, however, the product lines 15 and 16 remain in the low voltage level, because the p-channel type field effect transistors 44 and 45 keep off in the presence of the high voltage level at the intermediate nodes 32 and 33. This fluctuation in voltage level on the product line 14 results in that the nmos 34 turn on for discharging the output signal line 8, however, no fluctuation takes place in the voltage level on the output signal line 9.
In this instance, the output signal line 8 is shifted to the low voltage level with the exception of the coexistence of the input signal lines 6 and 7 in the high voltage level. In other words, the input signal on the signal line 6 is ANDed with the input signal on the signal line 7 to produce the output signal on the signal line 8. On the other hand, the signal line 9 goes down to the low voltage level in the coexistence of the input signals in the low voltage level, however, the high voltage level takes place on the output signal line 9 when at least one input signal remains in the high voltage level. Then, the output signal line 9 is used for the OR operation on the input signals. Though not shown in the drawings, various Boolean operations such as, for example, the NOR operation are further achieved on the basis of the AND operation as well as the OR operation.
A problem is encountered in the prior-art programmable logic array in that a huge field effect transistors should be installed to form the inverter circuit 46. This is because of the fact that the inverter circuit 46 should not only charge up an extremely large parasitic capacitance coupled to the control signal line 5 but also discharge the accumulated charges. In detail, as to the parasitic capacitance related to the product line 11 only, the inverter circuit 46 is expected to charge the source junction capacitance of the nmos 28, the gate capacitance of the nmos 28, the drain junction capacitance of the nmos 28, the gate capacitance of the pmos 31 and the drain junction capacitance of the pmos 37. Assuming now that the number of the product lines related to the OR plane 17 is Np, the amount of the total parasitic capacitance C5 coupled to the control signal line 5 is given by the following equation EQU C5=Np(Cs28+Cg28+Cd28+Cg43+Cd37)
where Cs28, Cg28 and Cd28 are the source junction capacitance, the gate capacitance and the drain junction capacitance of each field effect transistor between the control line 5 and each of the intermediate nodes, Cg43 is the gate capacitance of each field effect transistor coupled between the power supply line 2 and each of the product lines 14 to 16, and Cd37 is the drain junction capacitance of each field effect transistor coupled between the power supply line 2 and each of the intermediate nodes. In order to charge up this extremely large parasitic capacitance, the field effect transistor serving as the inverter circuit 46 needs to have a broad channel width, and, for this reason, a large amount of area is consumed by formation of the inverter circuit 46. On the other hand, if the inverter circuit 46 is small in size, a long time period is consumed for each access due to the small current driving capability of the small driver transistor. In other words, there is a trade-off between the operation speed and the occupation area for the inverter circuit 46.